RF amplifiers are utilized for a variety of applications in wireless communication systems, such as to amplify or transmit a downlink signal at a base station. As a result, the amplifiers must be able to handle the power requirements associated with such wireless communication systems. Some wireless applications have high peak-to-average signal ratios, and those amplifiers used for applications having high peak-to-average signal ratios must be able to handle or deliver significant peak power levels above their normal or average load. For example, in order to amplify a signal with a 10 dB peak-to-average ratio, while creating a minimal amount of non-linear distortion, an amplifier must be capable of delivering around 200 watts of power to generate an output signal with an average power of 20 watts.
The transistors used for the amplification in wireless RF amplifiers actually run most efficiently when they are outputting close to their maximum power capability, or are operating in a saturated mode. However, saturation also leads to signal distortion. Typically, the closer to saturation an amplifier is operated, the greater the amount of nonlinear distortion it outputs. Therefore, it has become standard practice to decrease or “back off” the amplifier power output of a particular amplifier until the nonlinear distortion is at an acceptable level. As a result, for handling high peak-to-average signal ratio applications in an amplifier, several amplification devices or amplifiers are usually operated together and have their outputs combined. In such an amplifier, the devices or sub-amplifiers are operated inefficiently most of the time at low power in order to be able to deliver, somewhat more efficiently, the maximum power for the relatively short period of time when the high peaks in the signal are to be amplified.
Techniques have been developed to improve linearity in order to more efficiently deliver the desired power requirements for certain wireless communication applications. Several linear circuit architectures familiar to those skilled in the art of amplifier design have been developed (e.g., feed-forward, cross-cancellation, pre-distortion, etc.). Furthermore, to improve the efficiency of such architectures, amplification design has employed numerous transistor technologies (e.g., LDMOS, GaN, SiC, and Bipolar, etc.), as well as various amplifier architectures (e.g., Doherty, LINC, Envelope Elimination and Restoration, Bias Adaptation, etc.).
The Doherty amplifier architecture improves amplifier efficiency by effectively reducing the amplifier's saturated power level when the signal level is low, yet quickly ramping up to full power capability when the signal peaks demand it. Classically, the Doherty design uses quarter-wavelength transmission lines as impedance transforming and inverting elements, which are somewhat large, and generally are not readily reduced for surface mounting on printed circuit boards. Additionally, in some instances these quarter-wavelength transmission lines may limit the bandwidth over which the amplifier can efficiently operate. Furthermore, it is often difficult to implement the classic Doherty design for low frequencies because of the physical size of quarter-wavelength transmission lines.
The parent application U.S. patent application Ser. No. 10/402,800 addresses various of the drawbacks of the prior art and provides efficient and linear amplification. However, it is still desirable to improve upon the design characteristics of such an amplifier for improving its fabrication, reliability and performance.
Accordingly, it is desirable to further improve the amplification schemes for RF applications associated with high peak-to-average signals ratio. It is also further desirable to address the drawbacks in the prior art by providing efficient and linear amplification, during both low power and high power peak requirements. These, and other objectives, are addressed by the invention described and claimed herein.